Reduced instruction set computer (RISC) architectures were developed as industry trends tended towards larger, more complex instruction sets. By simplifying instruction set designs, RISC architectures make it easier to use techniques such as pipelining and caching, thus increasing system performance. By focusing on speed and simplicity of design, rather than instruction semantics, RISC architectures often result in larger executable code size than comparable complex instruction set computer (CISC) architecture machines. For example, a task that may be represented as one complex instruction in a CISC architecture may take two or more instructions in a RISC architecture. However, the performance gains resulting from increased clock speeds and increased pipelining that may be attained with a RISC architecture usually outweigh any increase in executable code size.
RISC architectures usually have fixed-length instructions (e.g., 16-bit, 32-bit, or 64-bit), with few variations in instruction format. For example, each instruction in an instruction set architecture (ISA) may have the source registers in the same location. For example, a 32-bit ISA may have source registers specified always by bits 16–20 and 21–25. This allows the specified registers to be fetched for every instruction without requiring any complex instruction decoding.